Data_Sheet_1_Engineering Tunneling Selector to Achieve High Non-linearity for 1S1R Integration.docx (1.72 MB)
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Data_Sheet_1_Engineering Tunneling Selector to Achieve High Non-linearity for 1S1R Integration.docx

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posted on 15.04.2021, 06:10 authored by Navnidhi K. Upadhyay, Thomas Blum, Petro Maksymovych, Nickolay V. Lavrik, Noraica Davila, Jordan A. Katine, A. V. Ievlev, Miaofang Chi, Qiangfei Xia, J. Joshua Yang

Memristor devices have been extensively studied as one of the most promising technologies for next-generation non-volatile memory. However, for the memristor devices to have a real technological impact, they must be densely packed in a large crossbar array (CBA) exceeding Gigabytes in size. Devising a selector device that is CMOS compatible, 3D stackable, and has a high non-linearity (NL) and great endurance is a crucial enabling ingredient to reach this goal. Tunneling based selectors are very promising in these aspects, but the mediocre NL value limits their applications in large passive crossbar arrays. In this work, we demonstrated a trilayer tunneling selector based on the Ge/Pt/TaN1+x/Ta2O5/TaN1+x/Pd layers that could achieve a NL of 3 × 105, which is the highest NL achieved using a tunnel selector so far. The record-high tunneling NL is partially attributed to the bottom electrode's ultra-smoothness (BE) induced by a Ge/Pt layer. We further demonstrated the feasibility of 1S1R (1-selector 1-resistor) integration by vertically integrating a Pd/Ta2O5/Ru based memristor on top of the proposed selector.

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